1. Field of the Invention
The present invention relates to an apparatus for analyzing a failure in a semiconductor wafer in which a plurality of chips each having a plurality of memory cells are formed, and a method thereof.
2. Description of the Background Art
A method of analyzing a failure in a semiconductor wafer in which a plurality of chips each having a plurality of memory cells (which are generally arranged in a matrix form of rows and columns) includes a method of testing an electric property of memory cells by a tester, indicating the resultant data in coordinate space of X (row) and Y (column) to produce a pattern of a failure (which is generally called a fail bit map (hereinafter referred to as an FBM)) corresponding to the cause of a failure, and estimating the cause of the failure using this FBM.
Therefore, the cause obtained with the FBM is a mere estimation of a three dimensional position of a failure and an electric abnormality at that position, that is, an estimation of what failure (such as leakage, open and short) is happening at which position.
In order to actually improve a failure, this is insufficient and the cause of a failure in a manufacturing process must be clarified.
A method based on the above consideration is proposed in Japanese Patent Laying-Open No. 6-275688.
This is a method in which physical inspection of foreign materials, defects and the like at a surface of a semiconductor wafer is carried out by a defect inspection apparatus for each process of a plurality of processes in a production line, an electric property of memory cells of each chip in the semiconductor wafer manufactured in the production line is tested by a tester to produce a fail bit data (FBM), the result of physical inspection of foreign materials, defects and the like is collated with the FBM, thereby estimating whether a failure is caused by foreign materials, defects and the like produced during the manufacturing process or not.
Accordingly, the cause of a failure is not always located at the position of the failure found by the test, and there are many cases where the cause of a failure is located at a position other than the position of the failure.
Furthermore, not all the foreign materials and defects produced during the manufacturing process cause a failure, and whether foreign materials or defects cause a failure or not depends on the position, size and the like thereof.
Consequently, in the method proposed in the above mentioned document, the position of a failure found from the test by a tester is merely collated with each of the positions of foreign materials, defects or the like, and therefore, sufficient failure analysis cannot be performed.